Synchronous random access memories (RAMs) are commonly employed in computer systems to operate as cache RAM for a microprocessor. Synchronous RAMs (usually static RAMs or SRAMs) operate according to the timing provided by a system clock. For example, read operations begin with an address being latched on a first clock cycle. Once the address is latched, row and column decoding functions are performed and data are presented to at an input/output (I/O) latch where they are latched on a subsequent clock cycle. Other synchronous functions include "burst" modes wherein, according to control inputs provided, a range of column addresses can be generated on every clock cycle following the initial latching of the address. To accomplish synchronous operation, the system clock is received by the RAM device and distributed to various circuits within, such as the address latch and I/O latch described above.
While synchronous memories provide many advantages, increasing clock speeds and advances in fabrication technology can adversely affect synchronous memory operation. As is well known in the art, long-distance interconnects and delays due to reduced geometry active devices can contribute to overall delay in the propagation of signals within a memory device. Such delays are always present between the point at which the clock signal is received and the point at which the clock signal is applied, and result in a phase shift between certain portions the memory device and the actual system clock. As semiconductor chips get larger with increased integration, and operating frequencies get higher, the percentage of the clock cycle lost to delays increases. Such a phase shift, if severe enough, results in timing errors as portions of the memory device are no longer synchronous with the rest of the system.
A prior art example of an internal clock timing arrangement is set forth in FIG. 1a. The example illustrates, in block diagram form, the timing scheme for synchronous burst SRAM 10. The SRAM 10 includes a clock routing circuit 12, an address latch 14, an X-Y decoding section 16, a burst counter 18, an I/O latch 20, an I/O buffer 22, and an output pad 24. The clock routing circuit 12 receives an external clock (CLK.sub.EX) and drives the address latch 14, the burst counter 18, and the I/O latch 20. For the example in FIG. 1a, a delay element (.delta.) is shown between the external clock input and the I/O latch 20 that is representative of the propagation delay or skew therebetween. The delay results in a delayed clock signal (CLK.sub.I/O) being received at the input of the I/O latch 20.
Set forth in FIGS. 1b and 1c are two timing diagrams illustrating the timing signals of CLK.sub.EX, CLK.sub.I/O, and the output data (shown as Dout) for the SRAM 10 of FIG. 1a. The SRAM 10 of FIG. 1a is synchronous with the rising clock edge of CLK.sub.EX and the total delay introduced into CLK.sub.I/O is shown as "td". If the size of the delay td is too great, timing errors can occur. For example, it is known in the prior art to latch a memory address on a first clock edge and then internally latch the corresponding output data on the following internal clock edge. After a time tz, the output data will be available for sampling at the output on a third clock edge. In order for proper sampling of the output data to occur the output data must have a sufficient setup time prior to the third external clock edge, "ts", and a sufficient hold time, "th", after the third external clock edge. FIG. 1b illustrates an example where td is small enough that the output data have a sufficient setup time. In contrast, FIG. 1c illustrates an example where td is large enough that the output data have an insufficient setup time.
While FIGS. 1a-1c set forth an example of a delay between the external clock and the latching clock signal at the input to the I/O latch, it is understood that similar delays can occur for other clocked portions of the RAM. For example, an unwanted delay between the external clock input and the input to the address latch would shift the actual address latching point. As a result, the address may not have an adequate hold time to be valid.
Clock skew is commonly reduced by efficient layout designs that minimize long-distance interconnects carrying clock signals. U.S. Pat. No. 5,367,490 issued to Akimoto et al. on Nov. 22, 1994 illustrates an SRAM design with an advantageous layout, as well as an apparatus for providing a read pulse with a variable delay and duration to maximize timing efficiency.
Other specialized synchronous memory architectures, such as "pipeline" designs provide increased performance, but are still limited by the propagation delay of the clock circuits therein.
Other memory designs, unrelated to synchronous RAMs, have addressed variable data signals with phase locked loop designs. For example, a phase locked input port for the reception of asynchronous serial data in a two-port RAM is set forth in U.S. Pat. No. 5,260,909 issued to David Davidian on Nov. 9, 1993.
While a number of approaches to improving clock performance in semiconductor devices exist in the prior art, these approaches all have limitations as to the amount of improvement they can provide. Thus it is desirable to provide a circuit to improve clock performance beyond the methods described above.